ECC203 Computer Architecture and Organization

Course Description

Overview of computer architecture and organization, performance evaluation, memory hierarchy, storage, input/output, multicores, multiprocessors and clusters.

Prerequisite: ECC001

Course Objectives

to give students a good understanding of the fundamental architecture and organization of the computers

Course Outcomes

Understand the computer architecture and organization principles
Understand how the processor operate
Understand and write programs in assembly language
Understand the memory organization
Understand the storage and other input/output topics
Understand the Multiprocessors
Measure and compare performances of different systems
Understand the interaction between hardware and software

Meetings

Class meets weekly on Mondays 13:00-14:50 and Tuesdays 15:00-16:50

Grading

The tentative point distribution is as follows.

Homework Assignments	30%
Midterm Exam	30%
Final Exam	40%

Policies

Late assignments will not be accepted unless an agreement is reached with the leturer.
I allow students to attend class at their own discretion. If you miss a class however, you are responsible for the materials covered.
The instructor reserves the right to make changes to the given syllabus as necessary. Students are responsible to be aware of changes announced in class and/or via the internet.
Cheating will not be tolerated.
The class grades will be assigned using the Near East University's grading scale.
Attacks performed against University/Lecturer resources are expressly prohibited.

Textbook

Patterson D.A. and Hennessy J.L., Computer Organization and Design,The Hardware/Software Interface, ARM Edition, Morgan Kaufmann, 2017

Companion website

Schedule

Week	Topic	Readings
1 and 2	Introduction Computer Abstractions and Technology HW#1	Chapter 1
3, 4 and 5	Instructions: Language of the Computer, [ARM Reference Data sheet] A Survey of RISC Architectures for Desktop, Server, and Embedded Computers HW#2	Chapter 2 Appendix D
6 and 7	Arithmetic for Computers The Basics of Logic Design HW#3	Chapter 3 Appendix A
8	Midterm Exam	Results
9 and 10	The Processor Mapping Control to Hardware HW#4	Chapter 4 Appendix C
11 and 12	Large and Fast Exploiting Memory Hierarchy HW#5	Chapter 5
13 and 14	Parallel Processors from Client to Cloud Graphics Processor Units HW#6	Chapter 6 Appendix B
15	Review of the Semester
16	Final Exam