COM454 Advanced Computer Architecture

Course Description

Fundamentals of Computer Design, Instruction set architectures, Classifications, RISC, CISC, VLIW, EPIC, Pipeline processors, Memory Hierarchy Design (caches, virtual memory), Parallelism, Instruction level Parallelism, Data level Parallelism, dataflow mechanisms.Vector processing, Thread level Parallelism, Multicore systems, Multiprocessors

Prerequisite: COM254

Course Objectives

To teach how to design an instruction set.
To learn MIPS assembly language programming
To teach basic techniques of pipelining.
To teach I/O sub-system
To teach hierarchical memory subsystems including disk subsystem, processor caches, virtual memory, memory error correction.
To teach multiprocessing and concurrency concepts.

Course Outcomes

Designs a single/multi cycle microprocessor which corresponds to a specific instruction set architecture.
Writes programs using MIPS instruction set.
Understand theI/O sub-system
Explains cache architectures and the related operation principles.
Understand the multiprocessing and concurrency concepts

Grading

The tentative point distribution is as follows.

Homework Assignments	20%
Midterm Exam	30%
Final Exam	50%

Policies

Late assignments will not be accepted unless an agreement is reached with the leturer.
I allow students to attend class at their own discretion. If you miss a class however, you are responsible for the materials covered.
The instructor reserves the right to make changes to the given syllabus as necessary. Students are responsible to be aware of changes announced in class and/or via the internet.
Cheating will not be tolerated.
The class grades will be assigned using the Near East University's grading scale.
Attacks performed against University/Lecturer resources are expressly prohibited.

Textbook

John L. Hennessy, David A. Patterson, Computer Architecture, A Quantitative Approach, 5/e, Morgan Kaufmann, 2011. Details, Companion web site.

Schedule

Week	Topic	Readings
1	Introduction, Fundamentals of Quantitative Design and Analysis [Slides]	Chapter 1
2	Memory Hierarchy Design [Slides]	Chapter 2
3	Instruction-Level Parallelism and Its Exploitation [Slides]	Chapter 3
4	Instruction-Level Parallelism and Its Exploitation, Mid-term Exam	Chapter 3, Chapter 1-3
5	Data-Level Parallelism in Vector, SIMD, and GPU Architectures [Slides]	Chapter 4
6	Multiprocessors and Thread-Level Parallelism [Slides]	Chapter 5
7	Warehouse-Scale Computers to Exploit Request-Level and Data-Level Parallelism [Slides], Review of the Semester	Chapter 6
8	Final Exam